A Power-on-Reset circuit (PoR) is an indispensable component of system on chip (SoC) application, which provides a reset signal to the digital state machine of the SoC during power up and supply brown out, so that the digital state machine of the SoC starts and operates in a controlled manner. A PoR should be designed keeping in mind a wide variation of supply rise and fall times so that all kinds of supply situations, where the SoC's state machine may malfunction, can be taken care of. The huge number of registers inside a digital state machine of a typical SoC can be satisfactorily put into their reset states if the reset pulse (an active low reset pulse is considered in the present discussion) width (PW_PoR) is wider than a minimum value and the available supply voltage at that time is more than a minimum voltage (Vcmos.min) as shown in FIG. 1. This is because, the reset signal has to propagate to all the registers located probably over a large Si area with considerable capacitive load and the available supply voltage at that time may not be high enough for a quick reset action to take place inside the individual register. For slow supply rise, the required reset pulse width can be maintained using a voltage detector circuit with a proper value of upper trip point (UTP) as shown in FIG. 1. After the power-up and during normal operation of the SoC, if the supply voltage falls slowly below the safe level due to a temporary power failure (slow brown out) and recovers afterwards, a voltage detector with a proper lower trip point (LTP) can detect this by producing a wide enough reset pulse as shown in FIG. 1. Thus in case of slow supply rise and fall, a voltage detector with proper set of trip points and hysteresis voltage (PoR_UTP-PoR_LTP), is sufficient to meet the SoC's supply monitoring requirements. In this case, the hysteresis voltage helps to remove unwanted oscillation on PoR output due to power supply ripple around the trip points as discussed in prior art, U.S. Pat. No. 6,683,481, the relevant teaching of which is incorporated herein by reference. The PoR circuits in prior art 2, U.S. Pat. No. 7,450,359, the relevant teaching of which is incorporated herein by reference in FIG. 4 and prior art 3, U.S. Pat. No. 7,436,226, the relevant teaching of which is incorporated herein by reference in FIG. 5 do not provide any such hysteresis voltage and can be troublesome in the above situation. Therefore, a first area of focus of the present invention is implementation of a positive feedback mechanism circuit for achieving well controlled hysteresis voltage between the trip points of the PoR.
On the other hand, during fast supply rise, after the supply voltage reaches its final value, PoR's output should remain in low state (for an active low reset) for a sufficient time to allow the reset signal to be propagated to all the registers inside the SoC. This reset duration may be insufficient, as shown in FIG. 2a, when a voltage detector with its embedded hysteresis is employed alone. The prior art 2 and art 3 are made with a voltage detector only, and thus may fail in this fast supply rise condition. This need can be fulfilled by a simple RC delay circuit placed just after the supply detector as discussed in prior art 1 and shown in a representative diagram in FIG. 3. After power up, during normal operation of the SoC, the PoR should not respond to the expected synchronous switching noise (SSN) due to synchronous operation of digital circuits. A simple RC delay circuit with proper bandwidth placed after the voltage detector works well in tackling SSN noise too. On the other hand, a PoR should produce a wide enough reset pulse if there is a momentary failure (short lived brown out) in the supply voltage level, which has full potential to push a digital state machine to garbage states, as shown in FIG. 2b. Generation of a reset pulse wider than the short lived supply brown out is not possible with the combination of a voltage detector and simple RC delay circuit as proposed in prior art 1. The reason is that the RC circuit equally delays falling (TDF) and the rising (TDR) edges coming out of the voltage detector as shown in FIG. 2b. So, there is a need of a new delay mechanism to address the issue of short lived supply brown out. Thus, a second area of focus of this disclosure is to present a low area CMOS circuit with asymmetric rise and fall delays to handle both the fast supply rise, SSN and short lived brown out cases.
Additionally, the supply voltage of SoCs in sub-65 nm technology has come down below 1.2V, where 40 nm node is being operated with 1.1V (+/−10%) and 28 nm with 1.0V (+/−10%). Thus PoR circuits, required for these SoCs, need to work at low supply voltage. A bandgap and comparator based PoR as presented in prior art 1 would be very difficult to design in such low voltages. Moreover, as bandgap and comparator based PoRs suffer from high power and area consumption, they would not be the prime choice in many low-power compact mobile device applications. In addition, recently dynamic voltage scaling (DVS) is widely used as one of the useful low power techniques. In a DVS technique, the SoC's supply voltage is scaled down as the operating speed requirement comes down. A PoR with a single set of trip points and hysteresis voltage may malfunction in a DVS environment. We should be able to dynamically adjust the PoR's trip points and hysteresis voltage according to the present operating voltage. Thus the third area of focus of this invention is to present a PoR with trip points and hysteresis voltage programmability.